1. Field of the Invention
The present invention relates to a block-matching motion estimation apparatus used with a linear systolic array architecture for a full-search motion estimation operation, or a hierarchical-search motion estimation operation.
2. Description of the Related Art
The motion estimation apparatus according to the prior art is limited in its search range. Therefore, the motion estimation apparatus according to the prior art has had problems in that it is incongruent with any system which must search a wide range. Therefore, in order to perform a motion estimation operation for a wide search range, it is desirable that a plurality of chips are used in parallel by dividing the total motion search areas, or it is desirable that the system is implemented based on a method that one chip repeatedly executes the search operation for each search area. However, under such a situation, there may arise problems in that hardware is very large in its size and time taken in performing such operations is very long.
Further, in the motion estimation apparatus according to the prior art, because the operation speed of internal operation elements is the same as the speed at which data is provided from outside, there may arise therein another problem in that the speed of the internal operation element is limited by the external data supplying speed.